Senior Design Verification Engineer
We are looking for Senior ASIC SoC Design Verification Engineers for some of the most prestigious clients in the world.
· 5-7+years’ experience required
· Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
· Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
· Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
· Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
· Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.
· Work with architects to determine the use-case scenarios to simulate